1. Field of the Invention
The present invention is related to semiconductor memory devices, and more particularly to the test and characterization of static memory cells and related interface circuits.
2. Description of the Related Art
A manufacturing defect which causes a memory cell load device to be non-functional is frequently difficult to test. Such a defective memory cell can be written and subsequently read successfully even without the missing load device. But if the delay between the write and the subsequent read is long enough, the internal node of the memory cell leaks down to a degraded high voltage level, and only then will the memory cell fail. The delay required to detect such a failure may easily reach tens of seconds (at room temperature), which is entirely inconsistent with the required economies of manufacturing test.
Various methods have been used to try to detect failing load devices within static memory cells. Some involve operating the entire integrated circuit at degraded power supply voltage levels. While this may be effective in reducing the static noise margin of the memory cell, and thus reducing the time necessary for a memory cell to fail when tested, the technique requires the remainder of the integrated circuit to reliably operate at voltage levels for which the peripheral circuits themselves may lose margin, thus endangering the usefulness of the test method. Improved methods are needed, especially for those memory arrays which may be incorporated or embedded within large, sophisticated integrated circuits such as microprocessors.
The stability of both resistor-load and full CMOS (PMOS loads) SRAM memory cells is investigated, and expressions for static noise margin derived, in Seevinck, et al., "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 5, pp. 748-54 (October 1987).
A systematic approach for failure analysis for yield enhancement and reliability improvement for BiCMOS SRAM memory cells is described in Hall, et al., "A Structured Approach for Failure Analysis of a 256K BiCMOS SRAM," Conference Proceedings of The Failure Analysis Forum for Microelectronics and Advanced Materials, pp. 167-76 (November, 1989).